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RC4 - Verilog

Project information

Verilog (and HLS, C++, Python) implementation of the RC4 stream cipher.

rc4 verilog hls

+ 2 more

29 Commits
1 Branch
0 Tags

README
MIT License

Created on

February 22, 2021

Copy SSH clone URLgit@gitlab.com:matthiaskonrath/rc4-verilog.git
Copy HTTPS clone URLhttps://gitlab.com/matthiaskonrath/rc4-verilog.git

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