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Retro-V

Project information

Retro-V is a SoftCPU in Verilog that implements RISC-V 32-bit architecture RV32I, but with 8-bit external bus

RISC-V RV32I retro

+ 2 more

55 Commits
1 Branch
1 Tag

README
Apache License 2.0

Created on

November 29, 2018

Copy SSH clone URLgit@gitlab.com:shaos/retro-v.git
Copy HTTPS clone URLhttps://gitlab.com/shaos/retro-v.git

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