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Fix codegen bugs around the `port` expression 2 of 2 checklist items completed!353
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Support parametrization of external Verilog entities 1 of 2 checklist items completed!352
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Draft: Doc comments 0 of 4 checklist items completed!313
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Draft: new register declaration syntax 0 of 3 checklist items completed!298
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Draft: Conditional register syntax 0 of 2 checklist items completed!292 master
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Allow pipeline methods 2 of 2 checklist items completed!213
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WIP: Wordlength inference/push the changes further 0 of 2 checklist items completed
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WIP: Add syntax for expressing the idea of ranges - this is however not respected in the typechecker yet 0 of 2 checklist items completed!204 master
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