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sdm845-6.2.0dc94ad01 · ·
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qcom-clk-for-6.3-2c1855dd0 · ·
Qualcomm clock driver updates for v6.3 Support for requesting the next power_off operation for a genpd to be synchronous is introduced, and implemented in the GDSC driver. To allow the GPU driver to request power_off to wait for the GDSC to actually collapse. Support for QDU1000/QRU1000 Global clock controller, SA8775P Global clock controller, SM8550 TCSR and display clock controller, SM6350 clock controller, nd MSM8996 CBF and APCS clock controllers is introduced.. Parent references are updated across a large number of clock drivers, to align with the design changes since those drivers where introduced. Similarly, test clocks has been dropped from a range of drivers. A range of fixes for the MSM8996 CPU clock controller is introduced. MSM8974 GCC is transitioned off the externally defined sleep_clk. GDSC in the global clock controller for QCS404 is added, and various parent definitions are cleaned up. The SDCC core clocks on SM6115 are moved for floor_ops. Programming of clk_dis_wait for GPU CX GDSC on SC7180 and SDM845 are moved to use the recently introduced properties in the GDSC struct. The RPMh clock driver gains SM8550 and SA8775P clocks, and the IPA clock is added on a variety of platforms. The SMD RPM driver receives a big cleanup, in particular a move away from duplicating declaration of identical clocks between multiple platforms. A few missing clocks across msm8998, msm8992, msm8916, qcs404 are added as well. Using devm_pm_runtime_enable() to clean up some duplication is done across SM8250 display and video clock controllers, SM8450 display clock controller and SC7280 LPASS clock controller. Devicetree binding changes for above mentioned additions and changes are introduced. Support for postponing clk_disable_unused() until sync_state was introduced, but later reverted again, awaiting an agreement on the solution. Lastly, a change to pad a few registers in the SM8250 DTS to 8 digits was picked up in the wrong tree and kept here, to avoid rebasing.
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qcom-clk-for-6.37935b534 · ·
Qualcomm clock driver updates for v6.3 Support for requesting the next power_off operation for a genpd to be synchronous is introduced, and implemented in the GDSC driver. To allow the GPU driver to request power_off to wait for the GDSC to actually collapse. clk_disable_unused() is altered, to not consider clocks which comes from a provider with sync_state defined. This makes it possible for individual clock drivers to invoke this process once all clients has been probed, avoiding the need for booting many systems with clk_ignore_unused. This is then enabled for SDM845 and SC8280XP clock controllers. Support for QDU1000/QRU1000 Global clock controller, SA8775P Global clock controller, SM8550 TCSR and display clock controller, SM6350 clock controller, nd MSM8996 CBF and APCS clock controllers is introduced.. Parent references are updated across a large number of clock drivers, to align with the design changes since those drivers where introduced. Similarly, test clocks has been dropped from a range of drivers. A range of fixes for the MSM8996 CPU clock controller is introduced. MSM8974 GCC is transitioned off the externally defined sleep_clk. GDSC in the global clock controller for QCS404 is added, and various parent definitions are cleaned up. The SDCC core clocks on SM6115 are moved for floor_ops. Programming of clk_dis_wait for GPU CX GDSC on SC7180 and SDM845 are moved to use the recently introduced properties in the GDSC struct. The RPMh clock driver gains SM8550 and SA8775P clocks, and the IPA clock is added on a variety of platforms. The SMD RPM driver receives a big cleanup, in particular a move away from duplicating declaration of identical clocks between multiple platforms. A few missing clocks across msm8998, msm8992, msm8916, qcs404 are added as well. Using devm_pm_runtime_enable() to clean up some duplication is done across SM8250 display and video clock controllers, SM8450 display clock controller and SC7280 LPASS clock controller. Devicetree binding changes for above mentioned additions and changes are introduced. Lastly, a change to pad a few registers in the SM8250 DTS to 8 digits was picked up in the wrong tree and kept here, to avoid rebasing.