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drm-next-5.3-2019-06-248ac875db · ·
drm-next-5.3-2019-06-24: amdgpu: - Fix a regression with uvd init on some older asics due to Navi merge - Disable gfx off on navi10 until it's ready
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drm-next-5.3-2019-06-22f3f48d73 · ·
drm-next-5.3-2019-06-22: amdgpu: - SR-IOV L1 policy fixes - Removed no longer needed vram_page_split module parameter - Add module parameter to override default ABM level - Gamma fixes - No need to check return values for debugfs - Improve HMM error handling - Avoid possible OOM situations when lots of thread are submitting with memory contention - Improve hw i2c access abritration - DSC (Display Stream Compression) support in DC - Initial navi10 support * DC support * GFX/Compute support * SDMA support * Power Management support * VCN support amdkfd: - Implement priority controls for gfx9 - Enable VEGAM - Rework mqd allocation and init - Circular locking fix - Fix SDMA queue allocation race condition - No need to check return values for debugfs - Add proc style process information - Initial navi10 support radeon: - No need to check return values for debugfs UAPI changes: - GDDR6 added to vram type query - New Navi10 details added gpu info query - Navi family added to asic family query
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sunxi-ng-parent-rewrite-part-1-take-289f27fb2 · ·
Allwinner sunxi-ng clk driver parent relation rewrite part 1 - take 2 The first part of ongoing work to convert the sunxi-ng clk driver from using global clock name strings to describe clk parenting, to having direct struct clk_hw pointers, or local names based on clock-names from the device tree binding. This is based on Stephen Boyd's recent work allowing clk drivers to specify clk parents using struct clk_hw * or parsing DT phandles in the clk node. This series can be split into a few major parts: 1) The first patch is a small fix for clk debugfs representation. 2) A bunch of CLK_HW_INIT_* helper macros are added. These cover the situations I encountered, or assume I will encounter, such as single internal (struct clk_hw *) parent, single DT (struct clk_parent_data .fw_name), multiple internal parents, and multiple mixed (internal + DT) parents. A special variant for just an internal single parent is added, CLK_HW_INIT_HWS, which lets the driver share the singular list, instead of having the compiler create a compound literal every time. It might even make sense to only keep this variant. 3) A bunch of CLK_FIXED_FACTOR_* helper macros are added. The rationale is the same as the single parent CLK_HW_INIT_* helpers. 4) Bulk conversion of CLK_FIXED_FACTOR to use local parent references, either struct clk_hw * or DT .fw_name types, whichever the hardware requires. 5) The beginning of SUNXI_CCU_GATE conversion to local parent references. This part is not done. They are included as justification and examples for the shared list of clk parents case.
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sunxi-clk-for-5.3-201906210814b467ec06 · ·
A few patches to fix two minor bugs, and to introduce a schemas for our device tree bindings.
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sunxi-config64-for-5.3-201906210813dae335bc · ·
Our usual bunch of arm64 defconfig changes, this time mostly to enable some missing drivers for the Allwinner A64.
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sunxi-h3-h5-for-5.3-2019062108129fbbbb7b · ·
This time we only have a single patch for our command branch between arm and arm64, a fix for the array syntax raised by our DT schemas.
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sunxi-dt64-for-5.3-2019062108089164665a · ·
Our usual bunch of arm64 DT changes, this time with: - Some fixes for the DT schemas that were added during this release - Wifi support for the H6 - LRADC suppport for the A64 - Some background work on A64 boards, to enable various devices such as touchscreens, PMIC, audio, wifi, etc. -
sunxi-dt-for-5.3-2019062108072269f0c1 · ·
Our usual bunch of patches: - Some work on the BPi M2-Berry to support various devices - Convert some bindings to a schema, and a lot of fixes reported by the schemas we introduced. - A few other fixes here and there -
qcom-arm64-for-5.32410fd45 · ·
Qualcomm ARM64 Updates for v5.3 * Switch to use second gen PON on PM8998 * Add PSCI cupidle states for MSM8996, MSM8998,and SDM845 * Add MSM8996 UFS phy reset controller * Add propre cpu capacity scaling on MSM8996 * Fixups for APR domain, legacy clocks, and PSCI entry latency on MSM8996 * Enable SMMUs on MSM8996 * Add Dragonboard 845C * Add Q6V5, GPU, GMU, and AOSS QMP node on SDM845 * Fixup CPU topology on SDM845 * Change USB1 to be peripheral on SDM845 MTP * Add PCIe Phy, RC nodes, ANOC1 SMMU, and RPMPD node on MSM8998 * Update coresight bindings for MSM8916 * Update idle state names and entry-method on MSM8916 * Add PCIe, RPMPD, LPASS, Q6, TCSR, TuringCC, PSCI cpuidle states, and CDSP on QCS404 * Add reset-cells property to QCS404 GCC node * Fixup s3 max voltage, l3 min voltage, drive strength typo, and s3 supply definition on QCS404-evb * Fixup ADC outputs and VADC calibration on PMS405
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pm-5.2-rc63e26c5fe · ·
Power management fix for 5.2-rc6 Prevent PCI bridges in general (and PCIe ports in particular) from being put into low-power states during system-wide suspend transitions if there are any devices in D0 below them and refine the handling of PCI devices in D0 during suspend-to-idle cycles.