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A collection of Perl scripts for digital design simulation and FPGA synthesis automation. It supports Verilog, VHDL and mixed language (Verilog + VHDL) designs.
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A Docker image with the ModelSim HDL simulator
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Flexible 16-bit cryptographic co-processor written in VHDL and Verilog. From Assigment EE540 DCU Master in Electronic and Computer Engineering
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