VHDL

A simple VHDL project to monitor a serial port for ongoing communication.

Estrin's scheme is an algorithm for numerical evaluation of polynomials.

The source code of all IEEE packages. Development of future opensource.ieee.org/vasg/Packages releases.

Generic UART with parity

Webpage: http://wilferciro.gitlab.io/sintel Documentation: https://sintel.readthedocs.io/en/latest/

Create fast Fourier transform (FFT) processing hardware for your FPGA or CPLD. Use this tool to create an FFT core of any width or length. Customize to your project's needs. FFT hardware is generated in the SystemVeilog (SV) hardware description language (HDL).