FPGA

A simple COMmunication BLOCK with well know interfaces in the FPGA side

A synchronous protocol for accessing an asynchronous digital Design-Under-Test (JTAG sans the hassles)

This project is about building Hack on real hardware as proposed in chapter 13 of the course nand2tetris using only FOSS, free and open source hard- and software.

Collection of utility modules written in Verilog

Set of simple modules to communicate via UART

Collection of simple interfaces for Digilent Pmods

Interface module for MCP4725 DAC

Encoder and decoder modules for infrared receivers, transmitters and remotes

Simple I²S Master

Set of simple modules to communicate via I²C Bus.

Verilog interface for HC-SR04 Ultrasonic Ranging Module

Hardware integer divider module

Pair of modules to calculate crc values sequentially

Collection of some simple AXI4-Lite slaves.

Custom AXI GPIO core with up to 32 input and 32 output ports

Implementation of MIX as proposed in "The Art of Computer Programming, Vol. 1" by Donald E. Knuth. Runs on iCE40-fpga using only FOSS Hard- and Software.

Containerized FlexLM license manager for Questa*-Intel® FPGA Edition Software.

Containerized Questa*-Intel® FPGA Edition Software.

Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).

Verible build container.