verilog

Combinational adder and multiplier modules for IEEE 754 single-precision and double-precision floating point format.

Este repositorio contiene un resumen de los trabajos y proyectos en los que he participado. This repository contains a summary of the works and projects in which I have participated.

Block-ram based AES-256 CTR CDL module and test software. This project has a detailed writeup on my website at https://alexrhodes.io/blog/post/39/

Verilog (and HLS, C++, Python) implementation of the RC4 stream cipher.

Newest version of microprocessor design for Artix-7 100 Digilent Arty board. Includes the migrated Python assembler code as well, and a assembly-language implementation of Conway's Game of Life coded for this design.

Webpage: http://wilferciro.gitlab.io/sintel Documentation: https://sintel.readthedocs.io/en/latest/

Create fast Fourier transform (FFT) processing hardware for your FPGA or CPLD. Use this tool to create an FFT core of any width or length. Customize to your project's needs. FFT hardware is generated in the SystemVeilog (SV) hardware description language (HDL).

Welcome to the repository for the VALE8x64 project.

A Simple MLP Neural Network for MNIST Dataset Using Verilog HDL

project for UT CAD ~ Fall 96