verilog

Me trying to write a Verilog parser using ANTLR3

A collection of Perl scripts for digital design simulation and FPGA synthesis automation. It supports Verilog, VHDL and mixed language (Verilog + VHDL) designs.

Final project for the MSc course of Laboratory of Advanced Electronics held in 2021 by Prof. Leonardo Ricci at the University of Trento.

Este repositorio contiene un resumen de los trabajos y proyectos en los que he participado. This repository contains a summary of the works and projects in which I have participated.

Block-ram based AES-256 CTR CDL module and test software. This project has a detailed writeup on my website at https://alexrhodes.io/blog/post/39/

Verilog (and HLS, C++, Python) implementation of the RC4 stream cipher.

Toolchain for simulating and building FPGA projects.

Newest version of microprocessor design for Artix-7 100 Digilent Arty board. Includes the migrated Python assembler code as well, and a assembly-language implementation of Conway's Game of Life coded for this design.

My CPU / Microcontroller

Experiments on building a processing unit. Arduino Nano for test patterns on ICs.

This project is about building Hack on real hardware as proposed in Chapter 13 of the course nand2tetris using only FOSS, free and open source hard- and software.

Automate building the tools from Project IceStorm

A Docker image with the ModelSim HDL simulator

Webpage: http://wilferciro.gitlab.io/sintel Documentation: https://sintel.readthedocs.io/en/latest/

A small stack machine. http://hotwolf.github.io/N1

ECE 6710 Project, Creating ASIC convolution engine

A 32-bit pipelined RISC-V CPU

Projeto do MI - Sistemas Digitais

Welcome to the repository for the VALE8x64 project.

Flexible 16-bit cryptographic co-processor written in VHDL and Verilog. From Assigment EE540 DCU Master in Electronic and Computer Engineering